compiles, but didn't yet tested in hardware

port a can only read and port b can only write

next step: implement ram functionality to continue debug

does not work yet, have to debug more.

pin assignments for spi missing (only set 3.3V CMOS logic)
spi read and write goes to the same memory, currently
spi does not reset after cs high

seems to work now with little bleeding.
should maybe compare this to other boards/implementations to see issues...

need to ensure high oe well befor and after addr change

strange error: line n shines darker in line n-1

preloaded image is read during synthesis from mem.mif, which can be generated with the makefile and genmem.py
you have to install srecord, it was the first/only tool i got working to generate a suitable preload file.